1. Field of the Invention
Embodiments of the present invention relate to a liquid crystal display device, and more particularly to a method of driving a liquid crystal display device.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) device controls light transmittance of liquid crystal cells in accordance with video signals to thereby display a picture. Among LCD devices, an active matrix LCD device has a switching device at each liquid crystal cell. The active matrix LCD device is advantageous for displaying a moving picture because of the control provided by the switching device. The switching device used for the active matrix LCD device may be, for example, a thin film transistor (TFT).
FIG. 1 shows a circuit diagram of a pixel in a liquid crystal display device in accordance with the related art. Referring to FIG. 1, the active matrix LCD device includes gate lines GL and data lines DL crossing each other. Each crossing of one of the gate lines with one of the data lines define a pixel. A liquid crystal cell Clc is provided at each pixel. The active matrix LCD device converts a digital input data into an analog data voltage based on a gamma reference voltage. The analog voltage is supplied to one of the data lines DL. A scanning pulse is concurrently supplied to one of the gate lines GL to thereby charge the liquid crystal cell Clc.
A gate electrode of the TFT is connected to the gate line GL while a source electrode thereof is connected to the data line DL. Further, a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc and to one electrode of a storage capacitor Cst. A common electrode of the liquid crystal cell Clc is supplied with a common voltage Vcom. The storage capacitor Cst can be charged with the data voltage provided from the data line DL when the TFT is turned-on. Thus, the storage capacitor Cst maintains a substantially constant voltage at the liquid crystal cell Clc.
The TFT is turned on by the scanning pulse applied to the gate line GL to provide a channel between the source electrode and the drain electrode thereof. Thus, the TFT supplies a voltage from the data line DL to the pixel electrode of the liquid crystal cell Clc. An alignment direction of liquid crystal molecules from the liquid crystal cell is changed by an electric field between the pixel electrode and the common electrode, thereby modulating an incident light.
FIG. 2 shows a schematic diagram of an LCD device in accordance with the related art. Referring to FIG. 2, the LCD device 100 includes an LCD panel 110 including a thin film transistor (TFT) that drives a liquid crystal cell Clc at a each crossing of one of data lines DL1 to DLm and one of gate lines GL1 to GLn, a data driver 120 supplying a data to the data lines DL1 to DLm of the liquid crystal display panel 110, and a gate driver 130 supplying a scanning pulse to the gate lines GL1 to GLn of the liquid crystal display panel 110. A gamma reference voltage generator 140 generates a gamma reference voltage to be supplied to the data driver 120. A backlight assembly 150 irradiates light onto the liquid crystal display panel 110. An inverter 160 inverts an alternating current to power the backlight assembly 150. A common voltage generator 170 generates a common voltage Vcom to be supplied to the common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110. A gate driving voltage generator 180 generating a gate high voltage VGH and a gate low voltage VGL to be supplied to the gate driver 130. A timing controller 190 controls the data driver 120 and the gate driver 130.
The LCD panel 110 has a liquid crystal material injected between two glass substrates (not shown). The data lines DL1 to DLm and the gate lines GL1 to GLn perpendicularly cross each other on the lower glass substrate of the LCD panel 110. A TFT is provided at each crossing of one of the data lines DL1 to DLm with one of the gate lines GL1 to GLn. The TFT supplies a data from the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scanning pulse.
The gate electrode of the TFT is connected to the gate lines GL1 to GLn while the source electrode thereof is connected to the data line DL1 to DLm. Further, the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and to the storage capacitor Cst. The TFT is turned on by the scanning pulse applied through the gate lines GL1 to GLn to the gate terminal thereof. Then, the TFT supplies a video data from the data line DL1 to DLm to the pixel electrode of the liquid crystal cell Clc.
The gamma reference voltage generator 140 receives a high-level supply voltage VDD to generate a positive gamma reference voltage RV1 and a negative gamma reference voltage RV2. The gamma reference voltage generator 140 provides the positive gamma reference voltage RV1 and the negative gamma reference voltage RV2 to the data driver 120.
The data driver 120 samples and latches a digital data, such as a RGB digital video data or a RGB digital image data, from the timing controller 190 in response to a DDC signal from the timing controller 190. Then, the data driver 120 converts the sampled digital data into an analog data voltage corresponding to a gray scale level at the liquid crystal cell Clc of the LCD panel 110 in accordance with the positive and negative gamma reference voltages RV1 and RV2 from the gamma reference voltage generator 140. Then, the data driver 120 supplies the analog data voltage to the data lines DL1 to DLm.
The gate driving voltage generator 180 is supplied with a high-level supply voltage VDD to generate a gate high voltage VGH and a gate low voltage VGL. The gate driving voltage generator 180 supplies the gate high voltage VGH and the gate low voltage VGL to the gate driver 130. Herein, the gate high voltage VGH is larger than a threshold voltage of the TFT provided at each pixel of the LCD panel 110 and the gate low voltage VGL is lower than the threshold voltage of the TFT.
The gate driver 130 sequentially generates a gate pulse as a scanning pulse in response to a GDC signal and a gate shift clock GSC from the timing controller 190. The gate driver 130 supplies the scanning pulse to the gate lines GL1 to GLn. The gate driver 130 determines a high level voltage and a low level voltage of the scanning pulse in accordance with the gate high voltage VGH and the gate low voltage VGL from the gate driving voltage generator 180.
The inverter 160 converts an internally generated square wave signal into a triangular wave signal, and then compares the generated triangular wave signal with a direct current (DC) voltage VCC from said system. Then, the inverter 160 generates a burst dimming signal proportional to a result of the comparison. Then, a driving integrated circuit (IC) (not shown) controls a generation of AC voltage and current supplied to the backlight assembly 150 in response to the burst dimming signal.
The backlight assembly 150 is provided at the rear side of the LCD panel 110. The backlight assembly 150 is powered by the AC voltage from the inverter 160. The backlight assembly 150 irradiates light onto the LCD panel 110. The irradiated light from the backlight assembly 150 is incident onto each pixel of the LCD panel 110 including the liquid crystal cell Clc therein.
The common voltage generator 170 receives a high-level power voltage VDD to generate a common voltage Vcom. The common voltage generator 170 supplies the common voltage Vcom to the common electrode of the liquid crystal cell Clc provided at each pixel of the LCD panel 110.
The timing controller 190 supplies a digital data, such as a digital video RGB data or a digital RGB image data, to the data driver 120. The digital data may be outputted by an image processing scaler (not shown) in a system such as a TV set or a computer monitor, etc. The timing controller 190 also generates a data driving control (DCC) signal and a gate driving control (DGC) signal using horizontal/vertical synchronizing signals H and V in response to a clock signal CLK. The timing controller 190 supplies the DDC and the GDC signals to the data driver 120 and the gate driver 130, respectively. The DDC signal may include a source shift clock (SSC), a source start pulse (SSP), a polarity control signal (POL), and a source output enable signal (SOE), etc. The GDC signal may include a gate start pulse (GSP) and a gate output enable signal (GOE), etc.
FIG. 3 shows a schematic description of a timing controller in accordance with the related art. Referring to FIG. 3, the timing controller 190 includes a first memory part 191, a second memory part 192, a clock generator 193, and a parallel-to-serial converter 194. Herein, the first memory part 191 stores an input data to be supplied to an odd-numbered data line. The second memory part 192 stores an input data to be supplied to an even-numbered data line. The clock generator 193 generates clock signals for controlling reading and outputting stored data from one of the first memory part 191 and the second memory part 192.
The clock generator 193 receives an input main clock (MAIN CLK) signal and generates four divided clock signals to control reading operations from the first and second memory parts 191 and 192. The clock generator 193 alternatively supplies the four divided clocks signals to the first and second memory parts 191 and 192. The four divided clocks signals control a reading operation of 72 bits of stored data from one of the first memory part 191 and the second memory part 192.
The first memory part 191 stores an 18-bit input data at each divided clock cycle. Thus, the first memory part 191 can store 72 bits of input data during a period of four divided clocks from the clock generator 193. Data stored in the first memory part 191 correspond to an odd-numbered data line.
Similarly, the second memory part 192 stores an 18-bit input data at each divided clock cycle. Thus, the second memory part 192 can store 72 bits of input data during a period of four divided clocks from the clock generator 193. Data stored in the second memory part 192 correspond to an even-numbered data line.
The parallel-to-serial converter 194 converts the parallel data read from one of the first memory part 191 and the second memory part 192 into a serial data. The serial data from the parallel-to-serial converter 194 is outputted to the data driver 120 (shown in FIG. 2). For example, each of the 72 bits of stored data in the first memory part 191 is outputted to the parallel-to-serial converter 194 in parallel with a corresponding one of the 72 bits of stored data in the second memory part 192.
In the related art LCD device, the timing controller 190 reads 72 bits of data into one of the first memory part 191 and the second memory part 192 during a period of four divided clock signals. Thus, the related art LCD device has a large blank section following a data enable signal.